Test MP+dmb.sy+pos-addr-[fr-rf]-ctrl-pos

AArch64 MP+dmb.sy+pos-addr-[fr-rf]-ctrl-pos
"DMB.SYdWW Rfe PosRR DpAddrdR FrLeave RfBack DpCtrldR PosRR Fre"
Cycle=Rfe PosRR DpAddrdR FrLeave RfBack DpCtrldR PosRR Fre DMB.SYdWW
Relax=
Safe=Rfe Fre PosRR DMB.SYdWW DpAddrdR DpCtrldR [FrLeave,RfBack]
Prefetch=0:x=F,0:y=W,1:y=F,1:x=T
Com=Rf Fr Rf
Orig=DMB.SYdWW Rfe PosRR DpAddrdR FrLeave RfBack DpCtrldR PosRR Fre
{
0:X1=x; 0:X3=y;
1:X1=y; 1:X5=z; 1:X8=x;
2:X1=z;
}
 P0          | P1                  | P2          ;
 MOV W0,#1   | LDR W0,[X1]         | MOV W0,#1   ;
 STR W0,[X1] | LDR W2,[X1]         | STR W0,[X1] ;
 DMB SY      | EOR W3,W2,W2        |             ;
 MOV W2,#1   | LDR W4,[X5,W3,SXTW] |             ;
 STR W2,[X3] | LDR W6,[X5]         |             ;
             | CBNZ W6,LC00        |             ;
             | LC00:               |             ;
             | LDR W7,[X8]         |             ;
             | LDR W9,[X8]         |             ;
Observed
    z=1; y=1; x=1; 1:X9=1; 1:X7=0; 1:X6=1; 1:X4=0; 1:X2=1; 1:X0=0;
and z=1; y=1; x=1; 1:X9=0; 1:X7=0; 1:X6=1; 1:X4=0; 1:X2=1; 1:X0=0;